An integrated circuit (IC) consists of electronic devices electrically connected by conductive wires called interconnect lines, or simply interconnects. The interconnects are typically patterned from conductive layers formed on or above the surface of a silicon substrate. Complex ICs include several layers or levels of interconnects spaced from one another by interlevel dielectric structures.
Integrated circuit designers typically work with building blocks including multiple components such as logic gates. In a similar manner, it is now possible for IC designers to take highly complex functional units or blocks, such as microprocessors, bus/network interfaces, and signal processors, and integrate them into an IC much like other less complex building blocks. Such functional units, commonly referred to as “cores,” are becoming increasingly available.
System-on-a-chip (SOC) technology takes the core concept one step further, including all necessary circuits (e.g., cores) for a complete system, such as a cell phone or a digital camera, on a single IC. For example, an SOC for a sound-detecting device might include an audio receiver, an analog-to-digital converter, a microprocessor, memory, and input/output logic—all on a single IC.
Most complex logic circuits are synchronous systems wherein operations of multiple subcircuits or functional units are orchestrated by one or more clock signals. Such clock signals impose timing constraints on the functional units. To help ensure a manufactured IC will perform one or more functions within timing constraints established by clock signals, timing analysis or verification is performed on the functional units individually and/or collectively during the design phase.
As a result of shrinking dimensions due to technology scaling, propagation delays of logic devices continue to decline. At the same time, however, signal propagation times of interconnects (i.e., interconnect delays) have not been reduced to the same degree as reduced dimensions lead to increased resistance and larger resistance-capacitance (RC) parasitic delays. As a result, interconnect delays have become a larger fraction of signal path delays. For technologies with minimum dimensions smaller than about 0.25 microns, interconnect delays become a major performance limiter for high frequency applications. Further, interconnects are also becoming the dominant factor in determining IC power dissipation.
FIGS. 1A–1B will now be used to illustrate a problem that arises when a circuit is designed using values of environment factors (e.g., process speed, power supply voltage, temperature, and the like) adequate to meet the performance requirements of a first application, and the values of the environment factors are subsequently changed to meet the performance requirements of a new application. FIG. 1A is a diagram of a first circuit path 100 including only devices (e.g., transistors) 102 between a pair of cycle boundary latches 104A and 104B, where a signal launched by the latch 104A is captured by the latch 104B one cycle of a clock signal later. FIG. 1B is a diagram of a second circuit path 106 including two interconnect lines (i.e., interconnects) 108A and 108B and a buffer 110 between another pair of cycle boundary latches 112A and 112B, where a signal launched by the latch 112A is captured by the latch 112B during the next cycle of the clock signal. The buffer 110 is included in FIG. 1B only to reflect the need to maintain signal integrity along the circuit path 106.
Environment factors influencing propagation times of signals traveling along the circuit paths 100 and 106 include process speed, power supply voltage, and temperature. For example, when process speed and/or power supply voltage is increased or decreased, the signal propagation time along the circuit path 100 expectedly decreases or increases, respectively, according to a process technology used to manufacture the devices 102. On the other hand, the signal propagation times (i.e., delay times) of the interconnects 108A–108B of FIG. 1B remain substantially constant, and largely determine the delay time of the path 106. As a result, the delay time along the path 106 remains substantially constant.
When a circuit including the paths 100 and 106 is designed using values of environment factors adequate to meet the performance requirements of a first application, and the values of the environment factors are subsequently changed to meet the performance requirements of a new application, the above mentioned problem arises. For example, when process speed and/or power supply voltage is increased, the signal propagation time of the circuit path 100 of FIG. 1A is expectedly reduced, allowing higher speed operation of the circuit. However, the substantially unchanged signal propagation time of the circuit path 106 of FIG. 1B may prevent higher speed operation of the circuit.
It would thus be advantageous to have a system and method for designing a circuit including multiple conductors wherein timing analysis performed at an operating point associated with a first application would also ensure adequate performance in a known or projected second application.